Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology have greatly increased demand for high-speed under various modes of operation of these SDRAM circuits. These SDRAM circuits must provide wide data paths of at least 32-bits for typical memory systems. Data flow at each bit position of a 32-bit data word must function under existing 1-, 2-, 4-, and 8-bit serial and interleaved burst modes at high system clock frequencies. At these high clock frequencies, however, there is insufficient time for each data bit to flow from a sense amplifier in a memory array to an output terminal. For example, at a clock frequency of 300 MHz, one data bit is produced at each bit position every 3.33 Ns. Moreover, if the data rate is doubled, and a data bit is produced at each edge of the system clock, only 1.67 Ns is available for each data bit. By way of comparison, a typical read array time, or time for one data bit to flow from a sense amplifier to an output buffer, may be 5.3 Ns. A typical write array time, or time for one data bit to flow from an input buffer to a sense amplifier, may be 9.5 Ns. Current JEDEC specifications for pipeline and 2-bit prefetch operation help reduce the data rate problem but cannot meet future demands. Moreover, future architecture requirements must continue to function under existing SDRAM operational modes.